FIG. 1A is a schematic diagram showing a conventional fractional-N PLL (phase-locked loop circuit). The fractional-N PLL includes: a phase frequency detector 10, a charge pump 20, a loop filter 30, a voltage-controlled oscillator 40, and a frequency dividing unit 45.
Firstly, a reference signal with a reference frequency Fref is derived from a reference oscillator (not shown). The reference signal and a frequency divided signal derived from the frequency dividing unit 45 are simultaneously inputted to the phase frequency detector 10. A phase difference signal is derived from the phase frequency detector 10 in response to the phase frequency detector 10 detecting the differences of the phase and frequency between the reference signal and the frequency divided signal, and the phase difference signal is further inputted to the charge pump 20. An output current is derived from the charge pump 20 according to the magnitude of the phase difference signal, and the output current is further inputted to the loop filter 30. The output current is smoothed by the loop filter 30 and converted to a voltage-controlled signal, and the voltage-controlled signal is further inputted to the voltage-controlled oscillator 40. A voltage-controlled output signal with a voltage-controlled frequency Fvco is derived from the voltage-controlled oscillator 40 according to the voltage-controlled signal.
The frequency dividing unit 45 further includes: a dual modulus divider 50 and a frequency dividing circuit 48. The frequency dividing circuit 48 further includes: a first frequency divider 60, a second frequency divider 70, and a RS Flip-Flop 80. The dual modulus divider 50, also called pre-scaled divider, functions to receive the voltage-controlled output signal having the voltage-controlled frequency Fvco and divide the voltage-controlled frequency Fvco by (N+1) or N accordingly to the logic level asserted at the control terminal of the dual modulus divider 50, wherein N is an integer. The control terminal of the dual modulus divider 50 is connected to the output terminal (Q) of the RS Flip-Flop 80, in other words, the divided value N or (N+1) adopted by the dual modulus divider 50 for dividing the voltage-controlled frequency Fvco is determined by the logic level of the signal derived from the output terminal (Q) of the RS Flip-Flop 80. The signal derived from the dual modulus divider 50 is inputted to the first frequency divider 60 and the second frequency divider 70 of the frequency dividing circuit 48. The first frequency divider 60, also called program counter, functions to divide the frequency of the signal derived from the dual modulus divider 50 by P, and output the frequency divided signal to the reset terminal (R) of the RS Flip-Flop 80; the second frequency divider 70, also called swallow counter, functions to divide the frequency of the signal derived from the dual modulus divider 50 by S, and output the signal derived from the second divider 70 to the set terminal (S) of the RS Flip-Flop 80, wherein P, S are integers and P is greater than S. The output terminal (Q) of the RS Flip-Flop 80 is connected to the reset terminal (reset) of the second frequency divider 70.
In one period of the P cycles (cycle number 1 to cycle number P) of the signal derived from the dual modulus divider 50, the divided value of the dual modulus divider 50 will be (N+1) between the cycle number 1 to cycle number S due to a logic-low signal is asserted at the output terminal (Q) of the RS Flop-Flop 80 in response to the set terminal (S) of the RS Flip-Flop 80 is not set by the second frequency divider 70; the divided value of the dual modulus divider 50 will be N between the cycle number (S+1) to cycle number P due to a logic-high signal is assert at the output terminal (Q) of the RS Flop-Flop 80 in response to the set terminal (S) of the RS Flip-Flop 80 is set by the second frequency divider 70.
After one period (P cycles), the reset terminal (R) of the RS Flip-Flop 80 is reset by the first frequency divider 60, accordingly a logic-low signal is asserted at the output terminal (Q) and the divided value of the dual modulus divider 50 will be back to (N+1) again.
According to the above description, an equation can be derived from the fractional-N PLL depicted in FIG. 1AFvco=[(N+1)S+N(P−S)]Fref which can be written as
            F      vco              F      ref        =            (              P        +                  S          N                    )        ·    N  in other words, the equivalent divided value of the frequency dividing unit 45 is
      (          P      +              S        N              )    ·      N    .  
The frequency dividing circuit 48 in FIG. 1A can be implemented by two frequency dividers only. FIG. 1B is a schematic diagram showing the circuit configuration of another conventional fractional-N PLL, wherein the frequency dividing circuit 49 includes a first frequency divider 62 and a second frequency divider 72. Similarly, if one period includes P cycles (cycle number 1 to cycle number P) in the signal derived from the dual modulus divider 50, the divided value of the dual modulus divider 50 will be (N+1) between the cycle number 1 to cycle number S (when the second frequency divider 72 counts to S) due to a logic-low signal is derived from the second frequency divider 72 and further inputted to the control terminal of the dual modulus divider 50; the divided value of the dual modulus divider 50 will be N between the cycle number (S+1) and cycle number P (after the second frequency divider 72 counts to S) due to a logic-high signal is derived from the second frequency divider 72 and further inputted to the control terminal of the dual modulus divider 50; the reset terminal (reset) of the second frequency divider 72 is reset by the first frequency divider 62 in the cycle number P (one period), and the divided value of the dual modulus divider 50 will be back to (N+1) again.
According to the above description, an equation can be derived from the fractional-N PLL depicted in FIG. 1B
            F      vco              F      ref        =            (              P        +                  S          N                    )        ·    N  in other words, the equivalent divided value of the frequency-dividing unit 45 is
      (          P      +              S        N              )    ·      N    .  
Furthermore, the voltage-controlled frequency Fvco of voltage-controlled output signal can be further controlled by changing the divided value S of the second divider 70 and 72 in FIG. 1A and FIG. 1B. And, This kind of fractional-N PLL is called a spread spectrum clock generator.
FIG. 2 is a diagram showing the voltage-controlled frequency Fvco of the voltage-controlled signal in a prior-art spread spectrum clock generator. Because the divided value is an integer N or (N+1) in the dual modulus divider 50, the phase jump of the voltage-controlled output signal must be a multiple of 360 degree when the voltage-controlled frequency Fvco changes. In other words, the voltage-controlled frequency Fvco has a relatively poor accuracy; accordingly the spread spectrum clock generator has a relatively high jitter value. Furthermore, the spread spectrum clock generator with the above-mentioned structure has a relatively poor resolution, for instance, the voltage-controlled frequency Fvco cannot be accurately controlled when the spread spectrum clock generator is operated at 3 GHz and has 2500 ppm spread frequency. Therefore, providing a spread spectrum clock generator having a relatively high accuracy of voltage-controlled frequency and a relatively low jitter value is the main purpose of the present invention.